Engine Sensor Simulation Card

Real-time HIL engine control unit testing

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What is the Engine Sensor Simulation Card?

The Engine Sensor Simulation Card is a customized version of Concurrent’s programmable FPGA card specially designed for hardware-in-the-loop engine control unit (ECU) testing. The card and its associated firmware can support two- and four-cycle engines with up to sixteen cylinders and four independent, variable-phase camshafts. Engine speeds up to 30,000 rpm with 0.001 rpm resolution can be simulated along with crank reverse rotation (idling stop).

In HIL engine testing, an ECU is connected to a real-time simulation computer that executes the engine model and evaluates the ECU’s operation. An engine ECU handles a wide variety of input and output control signals that perform on the microsecond level. A single high-performance FPGA card, with its customizable firmware, can often provide an interface to the ECU that would otherwise require multiple standard data acquisition cards. An FPGA I/O card can also buffer ECU events to provide improved performance communication to and from the simulation model.

FPGA Card

Specifications

Firmware

Crank-Angle Sensor Signal Generation

Arbitrary Pulse Pattern Configuration with less than 0.006° CA Resolution at +30,000 RPM

Waveform generation identifiable by crank reverse rotation

Phase Shifting Output (A/B-Phase)

Multi-level Voltage Output

Pulse Frequency Modulation Output

Cam-Angle Sensor Signal Generation

Waveforms up to 4 shafts

Arbitrary Pulse Pattern Configuration with less than 0.006° CA Resolution for each shaft

Synchronization with Crank-Angle

Individual Phase Variable Command for all shafts (resolution 0.01° CA)

Ignition Signal Acquisition

Up to 16 channel inputs

Acquire the leading/trailing-edge timing of Crank-Angle sensor base

Minimum pulse width 50 nanosecs

Multiple pulses can be buffered

Fuel Injection Signal Acquisition

Up to 16 channel inputs

Acquire the leading/trailing-edge timing of Crank-Angle sensor base

Minimum pulse width 50 nanosecs

Multiple pulses can be buffered

Operation from SIMulation Workbench configuration

I/O configuration independent of modeling tools

Hardware

96-channel Digital I/O

5V 4mA TTL (3.3 Available)

Digital I/O Direction per Nibble

High Speed Digital Isolators

16-channel 16-bit D-to-A Conversion

Single-ended Output

0 to +10V, +/-5V or +/-10V Output

Range Selection

10 Milliamp Output Drive

100K Updates/sec per channel

16-channel 16-bit A-to-D Conversion

Differential or Single-ended Input

+/-5V or +/-10V Input Range

300K Updates/sec per channel

Altera Arria V Family FPGA

362K Logic Elements

DRAM

1GB

Other

TCXO Clock Source

8-output Programmable Clock Generator

Industry Standard SCSI 68-pin VHD Connectors for I/O

RJ-45 Connectors for Multi-board Synchronization

PCI Express x4 Revision 1.0a

Isolated Power on all I/O

Optional NIST Traceable Calibration

Packaging

DimensionsFHFL PCI Express (12.3″ long x 3.8″ high)

Power Requirements

Power Requirements

Up to 25 watts without external power connector

Up to 60 watts with external power connector

Environmental

Operating Temperature10° to 40° C
Storage Temperature-40° to 65° C
Relative Humidity10 to 80% non-condensing
CoolingForced Air Required
OtherROHS Compliant

Ordering Information

Engine Sensor Simulation CardCP-ENG-SIM
RedHawk Linux DriverWC-CP-FIO
SIMulation Workbench LicenseICS-SWB-1277

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